๐ Key Takeaways
- The October 2022 and October 2023 US export control packages targeted China's access to advanced AI chips (A100/H100 class and beyond). Enforcement gaps โ third-country transshipment, cloud access workarounds, and pre-ban stockpiling โ kept compute flowing longer than intended.
- Huawei's return as a credible AI chip maker (Ascend 910B/C), combined with DeepSeek's algorithmic efficiency breakthrough, fundamentally altered the strategic calculus: China is learning to do more with less compute.
- Beijing's response is not improvised โ it is a structured national program targeting full-stack AI independence by 2030, encompassing chips, foundry process, EDA tools, and operating systems.
1. The Controls โ What Washington Actually Did
On October 7, 2022, the Biden administration's Bureau of Industry and Security (BIS) published what many called the most sweeping export control package in American history. The regulations effectively banned the export of advanced AI accelerator chips โ primarily NVIDIA's A100 and H100 โ and the equipment needed to manufacture chips at or below 16nm logic, to China and a handful of other countries.
The policy was built on a theory of technological leverage: that AI capability is fundamentally constrained by raw compute, and that cutting China off from the world's best chips would impose a multi-decade delay on its AI development. If America and its allies held the high ground of leading-edge semiconductor manufacturing (Taiwan's TSMC, South Korea's Samsung, the Netherlands' ASML), China could be frozen at the sub-frontier indefinitely.
October 2023: Tightening the Net
One year later, recognizing that NVIDIA had designed around the initial controls with downgraded products (the A800 and H800, which technically met the performance thresholds but remained highly capable for AI training), BIS tightened the rules substantially. The October 2023 update imposed performance density limits, extended controls to more countries, and added licensing requirements for cloud computing access to controlled chips โ attempting to close even virtual compute loopholes.
The Trump administration, returning to power in January 2025, continued and in some areas extended the control framework, adding restrictions on AI model weights and expanding the entity list. By early 2026, the export control architecture covered chips, manufacturing equipment, EDA software, cloud access, and the models themselves โ a near-total siege of the AI technology stack.
The Control Architecture โ What Is Actually Restricted
Layer 1 โ Chips: AI accelerators above a compute performance ร interconnect bandwidth threshold. NVIDIA H100/H200/B100 series; AMD MI300X; and effectively all frontier AI training hardware.
Layer 2 โ Manufacturing Equipment: ASML EUV lithography machines (restricted since 2019); deep-UV systems below certain node sizes; deposition, etch, and metrology tools from Applied Materials, Lam Research, KLA Corp.
Layer 3 โ EDA Software: Synopsys, Cadence, and Mentor (Siemens) tools required for chip design at advanced nodes โ though enforcement here has been weakest.
Layer 4 โ Cloud Compute: US hyperscalers (AWS, Azure, GCP) prohibited from providing virtual access to controlled chips to Chinese entities without licenses โ though third-country cloud providers remain a gray area.
2. The Loopholes โ How Chips Kept Flowing
Despite the breadth of the controls, multiple vectors kept advanced compute flowing into China โ some openly, some through deliberate regulatory arbitrage, and some through outright circumvention that enforcement agencies struggled to track at scale.
3. The Huawei Comeback โ A Shock Nobody Anticipated
In August 2023, Huawei quietly launched the Mate 60 Pro smartphone in China. Teardown analysis by TechInsights and others revealed something that stunned analysts in Washington and Tokyo alike: the device contained a 7nm process chip โ the Kirin 9000s โ manufactured by SMIC, China's leading domestic foundry, without access to ASML's EUV lithography systems.
SMIC had achieved 7nm production using older deep-UV (DUV) multiple-patterning techniques โ a far more complex and expensive manufacturing process than EUV-based production, with lower yields and higher per-chip cost, but a working 7nm chip nonetheless. This single data point demolished the assumption that controlling EUV access would keep China locked at 28nm or above for the foreseeable future.
The Ascend 910 Series: China's Answer to the H100
More significant for AI than any smartphone chip is Huawei's Ascend 910B, a dedicated AI training accelerator designed in-house by Huawei's HiSilicon subsidiary. The 910B achieves approximately 256 TFLOPS of FP16 performance โ roughly 60% of the NVIDIA H100's 312 TFLOPS โ while running on SMIC's N+2 (approximately 7nm) process. The follow-on Ascend 910C, reported to be in sampling as of early 2026, is expected to close this gap further.
Chinese hyperscalers and AI labs have been ordering the 910B in quantity since late 2023. Baidu, Alibaba Cloud, and ByteDance are all reported to have deployed Ascend clusters for both training and inference workloads. The chips require more energy than their NVIDIA counterparts per FLOP and yield quality varies, but for a domestically produced alternative with no export control restrictions, they represent a dramatic achievement.
Chip Capability Comparison: 2026 Landscape
| Chip | Maker | Process Node | FP16 TFLOPS | HBM Memory | China Export Status |
|---|---|---|---|---|---|
| H100 SXM5 | NVIDIA (TSMC 4nm) | 4nm | 312 | 80 GB HBM3 | ๐ซ Banned |
| H200 | NVIDIA (TSMC 4nm) | 4nm | ~380 (est.) | 141 GB HBM3e | ๐ซ Banned |
| A100 | NVIDIA (TSMC 7nm) | 7nm | 312 (BF16) | 80 GB HBM2e | ๐ซ Banned (Oct 2022) |
| Ascend 910B | Huawei / SMIC N+2 | ~7nm | 256 | 64 GB HBM2e | โ Domestically Available |
| Ascend 910C | Huawei / SMIC N+2+ | ~6nm (est.) | ~320 (est.) | 96 GB (est.) | ๐ In sampling (2026) |
| Cambricon MLU590 | Cambricon / TSMC* | 7nm | ~180 | 32 GB HBM2e | โ ๏ธ TSMC access at risk |
| Biren BR100 | Biren / TSMC* | 7nm | ~256 | 64 GB HBM2e | โ ๏ธ Entity-listed, TSMC cut off |
* TSMC has ceased accepting orders from entity-listed Chinese chip designers following US pressure in 2023โ2024.
4. The DeepSeek Moment โ Efficiency as the Great Equalizer
If Huawei's Mate 60 Pro was the hardware shock of 2023, the software shock came in January 2025: the public release of DeepSeek R1, a reasoning-optimized large language model from a Hangzhou-based quant fund's AI subsidiary that performed on par with OpenAI's o1 on major benchmarks โ while reportedly trained at a fraction of the cost.
DeepSeek's disclosed training cost for an earlier model, DeepSeek-V3, was approximately USD 5.6 million โ a figure that stunned an industry accustomed to training frontier models for hundreds of millions of dollars. While the figure has been debated (it likely excludes significant pre-training compute and infrastructure costs), the underlying technical achievements โ Mixture-of-Experts architecture, multi-head latent attention, and aggressive FP8 mixed-precision training โ were real and reproducible.
๐ก Why DeepSeek Changed the Strategic Equation
Prior to DeepSeek, the dominant strategic assumption was that frontier AI required astronomical compute: the more H100 clusters you could run, the better your models. This assumption underpinned the entire export control logic โ deny China the chips, and you deny China frontier AI.
DeepSeek's efficiency innovations demonstrated that algorithmic breakthroughs can partially substitute for raw compute. A team working with constrained hardware budgets โ partly because US sanctions forced them to be creative โ discovered training and inference optimizations that are now being adopted by US labs themselves. The sanction-induced constraint accelerated, rather than retarded, certain lines of research.
This does not mean compute doesn't matter โ it still does, enormously. But it means the linear relationship between "chips denied" and "AI capability denied" is weaker than the control architecture assumed. China is not going to fall behind by a fixed multiple of its hardware disadvantage; it is actively narrowing that disadvantage through software innovation.
5. SMIC's Foundry Progress and the Road to 5nm
The bottleneck in China's hardware independence is not chip design โ Huawei's HiSilicon has demonstrated world-class design capability โ it is manufacturing. SMIC's N+2 (nominally 7nm) process works, but at materially lower yields and higher costs than TSMC's N5/N4 process or Samsung's 4nm, both of which use EUV lithography that China cannot access.
The key question is whether SMIC can push below 7nm without EUV. The physics are brutal: achieving smaller feature sizes with DUV multiple-patterning requires exponentially more process steps, each introducing defect risk. Industry analysts estimate SMIC's cost per wafer at 7nm is 40โ60% higher than TSMC's equivalent, and wafer-level yields are estimated at 60โ70% versus TSMC's 90%+. This cost disadvantage is significant but not prohibitive for a state-subsidized program.
The N+3 and N+4 Roadmap
SMIC is reported to be developing N+3 (approximately 5nm equivalent) and N+4 (approximately 3โ4nm equivalent) nodes, targeting 2027 and 2029 respectively. These timelines are widely viewed as ambitious. Industry veterans note that each new node generation with DUV multiple-patterning requires doubling the number of lithography passes, dramatically increasing complexity. The yield challenge at 5nm without EUV may prove intractable โ or it may require innovations in process chemistry and metrology that Chinese semiconductor equipment makers are racing to develop.
โ ๏ธ The AMEC, Naura, and YMTC Factor
China's domestic semiconductor equipment industry โ long dismissed as trailing international peers by 10+ years โ has shown surprising progress. Advanced Micro-Fabrication Equipment (AMEC) now sells etch tools used in SMIC's leading-edge production lines. Naura Technology has commercially deployed PVD and CVD tools at competitive specifications. And YMTC (memory) has achieved 232-layer 3D NAND production, demonstrating that given enough capital and time, Chinese companies can navigate around equipment restrictions. The question is not whether China can catch up, but when.
6. China's Full-Stack AI Independence Roadmap โ 2026 to 2030
Beijing's response to the export control regime is not ad hoc โ it is a structured national program articulated across multiple policy documents, including the "New Generation AI Development Plan" (2017, updated 2023), the "14th Five-Year Plan for the Digital Economy," and a classified "semiconductor sovereignty" roadmap that has been partially described in state media and government procurement announcements.
The Six Pillars of AI Sovereignty
- Compute: Huawei Ascend + SMIC domestic foundry, supplemented by continued overseas chip acquisition through all available channels.
- Memory: CXMT (domestic DRAM) and YMTC (3D NAND) are the critical suppliers; HBM-class memory remains a gap that CXMT is working to close.
- EDA Tools: Empyrean (ๅๅคงไนๅคฉ), Primarius, and several state-backed startups are developing domestic EDA suites โ currently viable for mature nodes but not yet competitive at 5nm design rule checking.
- Manufacturing Equipment: AMEC, Naura, SMEE (domestic lithography), and a dozen smaller companies are targeting the entire process equipment stack. The critical gap is EUV, where domestic alternatives are 7โ10 years behind ASML.
- AI Frameworks and Compilers: PaddlePaddle (Baidu), MindSpore (Huawei), and MegEngine (Megvii) are mature frameworks. Huawei's CANN compiler stack now supports Ascend chips with PyTorch-compatible interfaces.
- Talent: China graduated more than 300,000 engineering PhDs in 2024. The return of overseas Chinese AI researchers โ partly accelerated by US immigration uncertainty โ has bolstered domestic talent pools significantly.
7. A Timeline of the Semiconductor War
8. What This Means for Japan โ Caught Between Two Poles
Japan occupies a uniquely exposed position in the semiconductor geopolitical confrontation. Japanese companies โ Tokyo Electron (TEL), Shin-Etsu Chemical, JSR, Sumco, Lasertec, and others โ are central nodes in the global chip supply chain. Tokyo Electron alone controls an estimated 30% of global coater/developer equipment sales, and Japan accounts for the majority of global silicon wafer supply.
Japan's Export Control Alignment with the US
In July 2023, the Japanese government implemented its own export restrictions on 23 categories of advanced semiconductor manufacturing equipment, aligning with US and Dutch controls. This was a significant geopolitical commitment: it effectively forced Japanese companies to choose the US alliance over continued Chinese market access in the most sensitive technology categories.
The business impact has been measurable. Tokyo Electron's China revenues fell from approximately 40% of total sales in FY2022 to around 27% in FY2025 โ a decline of more than ยฅ300 billion at constant exchange rates. Kokusai Electric, a leading CVD tool maker, has similarly seen China-related revenues decline sharply. The companies have offset some of this through expanded US and Taiwan/Korea orders, but the transition has been painful.
The Opportunity Side: China's Domestic Equipment Drive Is a Market
There is a counterintuitive dimension: China's determination to build a domestic semiconductor equipment industry creates demand for materials, components, and subsystems that Chinese firms do not yet produce. Japanese specialty chemical companies, precision optics makers, and ceramic component suppliers occupy niches far down the supply chain from the restricted "end items" โ and many of these components remain exportable, for now, while commanding premium prices from Chinese buyers eager to reduce dependence on any overseas supply.
๐ก Japan's Strategic Dilemma
Japanese semiconductor equipment and materials companies are being asked to sacrifice significant China revenues in service of a US-led technology containment strategy whose long-term efficacy is increasingly questioned โ precisely because China's self-sufficiency drive appears to be working faster than expected.
If China achieves meaningful AI chip independence by 2030, Japanese companies will have absorbed the near-term revenue pain of export controls without the long-term benefit of sustained Chinese market access through continuing chip dependence. This calculus makes the semiconductor export control policy controversial within Japan's corporate establishment, even as the government remains publicly committed to US alignment.
9. Risk Scenarios โ Three Futures for the Silicon War
Scenario A: Controls Work Slower Than Expected โ Chinese Parity by 2030 (Base Case)
China achieves approximate AI chip parity with current-generation (2025) US technology by around 2030, maintaining a 3โ4 year trailing edge in the most advanced capabilities. State AI programs operate self-sufficiently on domestic hardware; commercial AI companies continue to use a hybrid of domestic and smuggled/stockpiled US hardware. The controls slow but do not stop China's AI progress. Global AI leadership remains contested.
Scenario B: A Breakthrough in Domestic EUV Accelerates Everything
If SMEE (ไธๆตทๅพฎ็ตๅญ่ฃ ๅค) or another Chinese entity successfully develops a viable EUV-equivalent lithography system โ an achievement most analysts rate as unlikely before 2033 โ the entire control architecture collapses. China could manufacture leading-edge chips at scale, and the foundry dependence that underpins the US-Taiwan-Japan-Netherlands export control coalition becomes irrelevant. This is a tail risk, but not a zero-probability one, given the scale of Chinese investment.
Scenario C: Controls Tighten Further, Triggering Formal Decoupling
If the US extends controls to DRAM, mature-node equipment, and EDA tools at currently-unrestricted nodes, and successfully coerces Japan and the Netherlands to follow, China responds with formal export restrictions on rare earth materials, graphite, and other inputs where it holds leverage. A bifurcated global technology supply chain crystallizes into two largely incompatible stacks. Japanese companies face the most difficult version of the dilemma: irrecoverable loss of China's massive market, or rupture of the US alliance.
10. Conclusion โ Containment or Catalyst?
The strategic logic of the October 2022 export controls was elegant: control the chokepoints in the semiconductor supply chain and you control the pace of AI development. Three and a half years on, the evidence is more ambiguous. The controls imposed real costs on China's AI ecosystem โ the absence of H100-class chips made certain training runs more expensive or slower. But they also concentrated Chinese engineering talent on the problem of working around hardware constraints, produced DeepSeek's algorithmic innovations, energized SMIC's process development program, and created massive state funding for a domestic chip industry that is, unmistakably, catching up.
The Great Silicon Wall is a real barrier. Chips do not flow as freely as before, and the gap between what TSMC can manufacture and what SMIC can manufacture remains meaningful. But walls slow; they rarely stop. China's AI independence is no longer a distant aspiration โ it is a national project with a timeline, a budget, and demonstrable milestones. The question for policymakers, investors, and businesses on both sides of the wall is not whether China will achieve AI self-sufficiency, but what the world will look like when it does.